This dissertation presents the design, implementation and validation of four multi- and single-die systems-on-chip (SoCs) for diagnostic and treatment of neurological disorders.

The first prototype is a multi-die wireless device that is designed and implemented as the first step toward a fully-integrated wireless brain machine interface SoC. The device is sized at 2 × 2 × 0.7 cm³, weighs 6 grams, and is comprised of two mini-boards and a power receiver coil. It takes advantage of two previously-reported chips (one on each board) as the core components for neural recording and stimulation, and for wireless data/power communication, respectively. The system is validated in:​ (a) in vivo detection and control of epileptic seizures in rats with temporal lobe epilepsy, and (b) sleep-stage classification and triggering responsive stimulation for REM (rapid eye movement) sleep suppression.

The second prototype is a 16 mm² 0.13 µm CMOS SoC. In this design, all the system-level functionalities of the above multi-die system (i.e. wireless data transmitters, wireless power receiver, signal processing unit for seizure detection, etc.) are integrated on a single die, and the AC-coupled recording channel is replaced with a chopper-stabilized digitally-assisted DC-coupled front-end. This is done by borrowing circuit blocks of three previously-reported chips (1. wireless power and data 2. DC-coupled front-end and 3. stimulator, and digital backend) and combining them on the same die. Channel-to-channel gain mismatch among the 64 channels of this chip is removed by utilizing a multiplying ADC, included in each channel, in a digital calibration loop.

The third prototype, which is the latest generation of responsive neurostimulator SoCs developed in our lab, features 64 correlated double-sampled ∆²∑-based (a ∆ stage and a ∆∑ stage) neural recording front-ends capable of recording brain signals with rail-to-rail DC offset variation. The mixed-signal design results in the channel area reduction by an order of magnitude (0.013 mm² for amplifier+ ADC+ stimulator), and channel power consumption being linearly scalable with the input signal frequency bandwidth. Additionally, using a current-output-DAC that is placed in the feedback path of the ∆²∑ ADC, a mixed-mode analog-digital multiplication is performed in each channel. This yields a compact implementation of band-pass digital filters, as well as voltage gain scaling. The analog multiplication circuit is reused as a current-mode stimulator when the SoC is configured to perform neurostimulation. The chip occupies 6 mm² and is validated in vivo in epileptic seizure monitoring, detection, and abortion.

The fourth prototype is a wireless 4-channel dual-mode arbitrary-waveform neurostimulator IC with 20 V voltage compliance. The system uses a load-aware adaptive supply voltage control, which results in up to 68.5% saving in power consumption. The 10 mm² SoC is implemented in a 0.35 µm HV-CMOS process. It is housed in a 2 × 2 × 0.7 cm³ multi-PCB device that also provides wireless power and data/commands telemetry for the chip. This design is preceded by the design of a board-level high-voltage hybrid 16-channel electrical and 8-channel optogenetic stimulator, validated in vivo for both its electrical and optogenetic stimulation functionalities.