CMOS remains the mainstream IC technology for the foreseeable future. This thesis addresses modeling and optimization of conventional and differential CMOS logic styles, provides insightful analysis, and derives formulas for optimal transistor sizing of mixed logicstyle CMOS circuits. Furthermore, as an application platform, the thesis deals with the less developed area of asynchronous circuits, rather than the commonly used synchronous circuits.

The scope of the modeling and optimization technique presented in this work covers the device, switch, logic, and module levels of abstraction. At the device level, we propose a simple model for evaluating the saturation current of submicron MOS devices. This model reproduces the short-channel characteristics of modern MOS transistors accurately. At the switch level, we recognize and model four types of delays:​ PMOS rising delay, NMOS falling delay, NMOS rising delay, and PMOS falling delay. The delay models at this level, capture the effect of input signal slope and characterize the behaviour of MOS transistors connected in series. At the logic level, we apply the switch-level delay models to formulate delay macromodels for different CMOS logic styles including conventional, DCVSL, and CPL. We also derive closed-form optimal transistor sizing formulas for several popular CMOS logic styles. At the module level, using the optimal transistor sizing formulas, we demonstrate that it is feasible to optimize the delay of a circuit involving mixed CMOS logic styles.

Part of this work is devoted to comparing different CMOS implementations of logic gates. We develop a fair method for this purpose and study the performance and energy consumption of various conventional and differential CMOS implementations of the C-element and XOR gate, which are the most widely used primitives in asynchronous control circuits. For each primitive, we express our recommendation regarding the most appropriate implementation. We also introduce a differential logic style that has a static memory and, hence, is suitable for implementing primitives such as the C-element.

Finally, a theory of delay optimization evolves from our work that states the delay in a cirC11.it consisting of conventional CMOS logic gates is minimal if for each stage along the critical path of the cirC'Uit, the delay due to that stage as a load equals the delay through that stage as a drive.