In this dissertation, the second generation design and implementation of a new type of computer arithmetic is explored. The approach used in this dissertation for binary computations is based on a novel number system called Continuous Valued Number System, where digits are continuous, and do not have a grid. Arithmetic operations in this number system are based on the modular reduction operations.

In this dissertation, actual implementation of adders and multipliers based on this new concept are developed. These systems are implemented by analog circuitry, and are based on the current-mode circuit design approach in CMOS technology. The current-mode approach provides efficient means for implementing low-power, and highly integrated designs based on this method of computation.

The almost carry-free nature of addition in the Continuous Valued Number System results in high performance analog adders, which becomes the main building block of more complex designs such as reconfigurable adders, tree and array multipliers. The implementations are compared with their binary counterparts, and results show that, the Continuous Valued Number System can open up a new path for advanced signal processing.

The Continuous Valued Number System is an analog number system, and due to data overlap between the digits, the general operations in this number system are more precise compared to regular analog systems. Therefore, new models for analog neurons are proposed which are based on the function evaluation properties of this number system. The stochastic modeling of the proposed neuron shows that our system can tolerate more implementation errors caused by noise or by nonlinearity in analog environments.

The work presented in this dissertation, paves the way for a new type of high performance computer arithmetic and advance signal processing.