In this dissertation some algorithms and related hardware structures for computing division and multiplication over finite or Galois fields are presented. The structures are regular, which is important for hardware realization, particularly for large finite fields.

The concept of supporting elements is introduced which leads to efficient algorithms for computing divisions and multiplications in finite fields. A relationship between systems of linear equations over GF(q) and division in GF(q^m) is established. Using this relationship, a division algorithm valid for any irreducible polynomial or any field basis is presented. It is also proved that if the elements are represented with respect to a canonical basis, then division over GF(q^m)] can be performed by solving a discrete time Wiener-Hopf equation over GF(q).

A bit-serial systolic divider for finite fields of the form GF(2^m) is presented. The divider structure does not depend on the irreducible polynomial defining the field and requires no global data communications. Moreover, the time step duration is independent of the value of m, which is important for large finite fields.

By exploiting the structure of a Toeplitz matrix, a bit-serial multiplier applicable to any irreducible polynomial defining the field is presented. The multiplier is efficient in the sense that it requires, in general, less circuitry compared to equivalent existing multipliers.

Finite fields GF(2^m) generated by irreducible all one polynomials (AOP) and equally space polynomials (ESP) are considered. Algorithms and structures are presented for parallel computation of multiplications in these fields. It is shown that if for a certain degree both an irreducible AOP and ESP exist, it is advantageous to use an ESP based parallel multiplier. Moreover, it is shown that parallel multipliers based on ESP can be obtained by using modules of a corresponding AOP based multiplier.

Finally, as an application of the efficient bit-serial multiplication algorithm, a Reed-Solomon encoder structure is presented. The structure features simple basis transformation circuitry and supports a variable code rate.