Compound codes developed over the past decade are increasingly being used for error control in data communications standards. As demand for throughput increases, the currently existing decoding architectures will no longer be practical for wireless applications due to their growing power consumption. New techniques based on analog and mixed-signal circuits are derived in this thesis.

Circuits for analog Viterbi detection are improved and used for soft-output forward-backward decoding of convolutional codes. The circuits are self-normalizing, and can be used with an arbitrary number of trellis stages or states. Architectures for programmable analog interleavers are introduced, some reducing size and capacitance by over 70% relative to full crossbar interleavers with 100 inputs. The soft-output and interleaver techniques are used in an analog turbo decoder test IC, with 4-state convolutional encoders with 16 information bits. The IC, designed in a 0.35μm 3LM CMOS technology, was tested at 13.3Mbps, 1.2μs latency, and consumes 185mW on a single 3.3V power supply, resulting in energy consumption of 13.9nJ per decoded bit, 80% better than published digital implementations. Swinging buffers could triple the speed and reduce the latency with minimal increase in power consumption. The core area is 1131.2 x 1257.9 μm².

Future error control codes and their corresponding hardware will be designed in a global manner, optimizing code performance and circuit specifications at the same time. A turbo-like code and its associated decoder, operating at very high speeds and low power consumption, is presented in this thesis. The code, inspired by analog architectures, also has very interesting digital decoder realizations that drastically reduce decoding latencies.