Field-programmable gate arrays (FPGAs) are a popular choice for digital circuit implementation because of their growing density and speed, short design cycle, and steadily decreasing cost. Power consumption, specifically leakage power, has become a major concern for the semiconductor industry and its customers. FPGAs are less power-efficient than custom ASICs, due to the overhead required to provide programmability. Despite this, power has been largely ignored by the FPGA research community, whose prime focus to date has centered on improving FPGA speed and area-efficiency. This dissertation presents new techniques for optimizing and predicting the power consumption of FPGAs.

First, two novel computer-aided design (CAD) techniques for FPGA leakage power reduction are presented. The proposed techniques are unique in that they substantially reduce leakage power, while imposing no cost, meaning that they have no impact on FPGA area-efficiency, speed, or fabrication cost.

Following this, the circuit-level design of low-power FPGA interconnect is considered. A family of new low-power FPGA routing switches is proposed. The switches significantly reduce dynamic and leakage power in the interconnect, with varying amounts of area and/or performance cost. The proposed switches require only minor changes to traditional FPGA routing switches, allowing them to be easily incorporated into current FPGAs.

Next, a new power-aware technology mapping algorithm for look-up-table-based FPGAs is described. The algorithm takes an activity-conscious approach to logic replication, and allows trade-offs between circuit performance and power. The dynamic power of mapping solutions produced by the proposed algorithm is shown to be considerably less than competing techniques.

Finally, the topic of early dynamic power estimation for FPGAs is addressed. Empirical models are developed for the prediction of interconnect capacitance and switching activity in FPGA designs. The proposed models can be applied early in the design process, when detailed routing data is incomplete or unavailable, thereby reducing design effort and cost.