New theoretical results concerning transistor circuits which exhibit the socalled negative differential resistance (NDR) behavior are presented. Such circuits find wide use in the design of memory elements, oscillators, signal detectors and switching devices. An NDR is realized by configuring a transistor circuit as a oneport having a nonlinear voltage vs. current relation which, in particular, is defined by a curve having a region with a negative slope. One of the fundamental properties of a transistor NDR circuit is that it provides the possibility of varying such characteristics as the shape and the location of the NDR region of the curve by simply adjusting the values of the circuit parameters.

It has previously been established that a specific topological entity called a feedback structure is essential for the NDR behavior of a transistor circuit. In addition, circuit parameters should have appropriate values for a prominent NDR behavior in a circuit. We thus examine the influence of such parameters as resistor values and transistor current gains on the shape of the curve which characterizes an NDR device. Moreover, we investigate the biasing conditions that circuit topology, parameter values and source values impose on transistor pn junctions, and establish necessary conditions for the occurrence of NDR phenomena. The circuit topology necessary for achieving these biasing conditions in circuits with bipolar transistors is also given.

We use our results to propose simple circuit models for the widely used Silicon Controlled Rectifier (SCR) device, and nonlinear latch-up phenomena which occur in CMOS VLSI circuits. These models employ two transistors and resistors only, and are capable of simulating SC/J-type dc behavior. They appear to be especially useful for computer-aided simulations.