The recent growth of data intensive multimedia-based applications has sustained the need for more efficient ways to encode signals and images. Over the years, the Discrete Cosine Transform (DCT) has emerged as the most popular transform for many image and video compression applications. Because of its enormous popularity, much research has been published on fast algorithms, where the effort is devoted to reducing the number of arithmetic operations used. In all the previous cases of finite-precision implementations, approximation is required to implement the real-valued irrational transform coefficients - this not only results in computational error throughout the transform process, but also limits the quality of the reconstruction process. An error-free encoding using algebraic integers, previously introduced by Vassil Dimitrov, has been shown to be an effective way of resolving the issue. This is a mapping technique that encodes the irrational transform basis functions using algebraic integers. The mapping scheme is referred to as Algebraic Integer Quantization (AIQ).

After the success of the previous schemes, this research extends the concept of error-free (infinite-precision) mapping and investigates novel AIQ-based architectures for the fast implementation of several 8x8 2-D scaled Discrete Cosine Transforms and Inverse scaled DCTs. A detailed discussion on the AIQ-based integer-like 8x8 2-D DCT for the H.264 standard, along its quantization and de-quantization stages, is also presented. Apart from the multiplication-free nature, this new mapping scheme eliminates any computational or quantization errors during the transform stage and resulting in hardware-efficient and high-speed designs that focus on real-time image or video compression and HDTV applications.

This research work also discusses VLSI implementations and architectures for these scaled and integer-like DCT algorithms. For FPGA implementations, both Xilinx and Altera cells have been used, whereas for the ASIC designs, TSMC Artisan 0.l8um library cells have been used. These new architectures have been shown to perform at a rate of 40% higher frequency and a hardware cost reduction of 30% compared to previously published architectures. Finally several finite wordlength simulations have been presented which show that the accuracy and the precision of the designed hardware fully comply with the IEEE implementation standard (for JPEG and MPEG-4 decoders).