A taxonomy of VLSI layouts are presented for the implementation of maximum likelihood sequence estimators realized by the Viterbi algorithm (VA), a dynamic programming solution to estimating a state sequence. These are classified in terms of increasing interprocessor wire area each of which are capable of increased data throughput. Cascade, Linearly and Orthogonally Connected Mesh, Shuffle-Exchange and Cube-Connected Cycle layouts can efficiently embed the VA in silicon. These structures are generalized to accommodate an arbitrary source alphabet size and algorithm memory length. The algorithm-structured layouts by implication are appropriate for convolutional decoding. The area * time and area * time('2) measures of complexity for the VA are presented and interpreted within the context of digital communications. One important result based on hardware considerations suggests that the algorithm memory length should be prime. Viterbi receivers for correlative encoded MSK, using first and second order encoding polynominals, are shown to reside in a generalized class of Cube-Connected Cycle layouts.

In addition, a Normalized Kolmogorov Metric Space is proposed which can be incorporated into the VLSI designs. Though the simulation results are preliminary, this new metric space may find application in suboptimal soft decision decoding schemes.