High-speed networks have become more and more popular worldwide driven by the Internet and its applications. Multicast has become a necessary feature for any switch designed for future broadband communication networks. In this dissertation, a multicast switch architecture called the Balanced Gamma (BG) multicast switch is proposed, analyzed and implemented. A comprehensive study of this promising multicast switch architecture has demonstrated its superiority in terms of loss performance, delay performance, and buffer requirement performance under various uniform and nonuniform traffic. At the same time, it is scalable, reliable, and fault-tolerant, and its hardware complexity is reasonably low which makes it feasible to build as a practical switch.

The new multicast BG switch fabric is characterized by its space-division architecture in which the control of cell routing is distributed over all switch elements. The key characteristic of a multicast switch, the cell replication function, is integrated into the routing function of the switch element. Two new algorithms are designed to support implicit cell routing and replication, namely the dynamic-length routing and replication algorithm and the dynamic-length backpressure algorithm. Topological equivalence to the unicast BG switch ensures that the new architecture inherits many attractive features such as reliability and fault tolerance from the latter.

A multicast traffic model is developed for the analysis of the multicast BG switch. The performance of the switch is examined under various traffic conditions, random and bursty, uniform and nonuniform. Numerous simulation trials are performed to obtain the loss, delay, and buffer requirement performance of the switch. An analytical model is derived under the multicast random traffic model to verify our simulation results. The discrepancy between the analytical model and simulation is justified and further improvement of the model is suggested. Performance results are also compared to that of the ideal multicast switch to demonstrate how close the performance of the BG multicast switch is to the optimum result. It is determined through the analysis that the multicast BG switch is a high performance switch in handling unicast, multicast, and mixed traffic. At the same time, it is scalable in terms of architecture, performance, and implementation.

Following the digital IC design methodology recommended by the Canadian Microelectronics Corporation (CMC) and using the VLSI CAD tools they have provided, a 16 x 16 switch fabric has been implemented using 0.18μm CMOS technology and the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL). It is demonstrated that the whole switching fabric module can be easily fit into a single IC chip with the current fabrication technology. Finally, the methodology of functional verification of the hardware design is presented and hardware complexity of larger switches is explored.