The complexity of digital logic systems has increased steadily and rapidly for the last several decades due to a steady trend in technology scaling. As current manufacturing technology reaches the deep-submicron level, an increasing amount of low-level design effort is required to create a working design. This further increases the cost and complexity of these designs.

One way to separate digital systems, design from the problems of deep sub-micron design is to use programmable logic device (PLD) technology. This provides a clean interface, allowing systems designers to stop at the RTL level while physical design issues are solved by the PLD designers. Although this is a very convenient abstraction, it suffers from significant inefficiencies in area and delay that make the approach unsuitable for many large systems.

This dissertation improves the area efficiency of PLDs by analysing the design of their largest components, the switch blocks and sparse crossbars found in the interconnection network. The approach taken is to modify their topological organisation, so that the routing network can be more highly utilised, as well as their circuit implementations, so they can be made smaller. Through transistor-level design, the delay of these circuit implementations is also reduced, particularly delay under fanout.

The improvements made to these network components can be applied to a variety of high-level PLD interconnect styles. In this dissertation, they are shown to improve area and delay in a mesh-style PLD architecture.